In recent times, manufacturing of semiconductor memory devices continuously advances toward high integration and high speed with development of technologies and such devices are used in a variety of products from large home appliances to small mobile products.
Address paths of semiconductor memory devices include a row address path through which a word line is selected by a row address and data stored in all cells connected to the selected word line are loaded on bit line pairs and amplified by a sense amplifier, and a column address path through which one of a plurality of the bit line pairs is selected by a column address and the selected data are read or written.
Also, such column address path is divided into a data access path through which one of a plurality of output enable signals is selectively enabled to select one of the plurality of the bit line pairs loading the data thereon, and a data transfer path through which the selected data are read or written. Among these, operation of controlling the data access path (hereinafter, referred to as ‘data access operation’) is performed by a data access control circuit, including a column decoder, that decodes the column address and selectively enables one of the plurality of output enable signals to allow the selected data to be read or written.
In general, a semiconductor memory device such as a DRAM includes a plurality of banks having respective memory cells to which a same address is assigned. This semiconductor memory device simultaneously outputs data in the memory cells of the same address included in each bank. To this end, the data access control circuit decodes the column address and selectively enables one of the plurality of the output enable signals, and performs operation of transferring the data loaded on the bit line pair selected in the bank enabled by the output enable signal.